FinFETs can be scaled down to 7 nm design rules and perhaps stretched to 5 nm design rules. Beyond 5 nm design rules, short channel effects degrade FinFET performance such that further scaling does not bring benefits. Some developers are considering Gate-All-Around nanowires, which could enable scaling down to ˜2 nm design rules.
FIG. 1 is a simplified perspective view of a conventional FinFET transistor 100. It comprises a semiconductor “fin” 110 extending in a longitudinal direction L. The fin also has a transverse direction T. The fin has drain and source regions 112 and 114 respectively, separated longitudinally by a channel region (hidden in the drawing). Drain and source contacts 116 and 118, respectively, are connected to the drain and source regions 112 and 114, respectively, and are separated longitudinally by a gate stack 118. The gate stack 118 may be a high-K metal gate (HKMG) layer (metal gate sub-layer separated in a vertical direction V from the channel region of the fin by a thin high-K gate dielectric layer 120. The gate stack 118 is separated longitudinally from each of the drain and source terminals 114 and 116 by dielectric spacer material 122.
One limitation on scaling of FinFETs and nanowires is that Middle-Of-Line (MOL) parasitic capacitance is increasing as 1/x with each technology generation, where x is the spacer width (in the transistor longitudinal direction), scaling as 0.7× per generation. MOL capacitance comes mainly from the gate 118 facing the drain contact 114 across the shrinking spacer 122. See the arrows 124 in FIG. 1. MOL capacitance is expected to overtake interconnect capacitance as the dominant load of the transistor at 5 nm design rules, and will continue increasing with further scaling.
Another limitation on scaling of FinFETs is that fin pitch scaling is limited by the multi-layer High-K dielectric+Metal Gate (HKMG) stack which requires consistent HKMG vertical thickness in order to maintain a consistent threshold voltage. Currently, the minimum HKMG stack thickness between the fins is approximately 14 nm and would require a new technology to shrink beyond that.
Yet another limitation on scaling of FinFETs is cross-sectional fin shape variability. It is difficult to enforce consistent fin shape, and fin shape variations introduce FinFET performance variations. For example, off-state current increases exponentially with increases in fin width. Performance variations lead to lower circuit performance and higher chip area and cost. It seems that new ideas will be needed in order to continue scaling transistors down to smaller and smaller sizes.